1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, which reduces the influence of electrical charges stored in a wafer by sputtering or dry etching or the like.
2. Description of the Related Art
In a wiring process subsequent to formation of a gate, there is generally a fear that when heat treatment is done at a high temperature, aluminum (Al), titanium (Ti), tungsten (W) or the like used as a wiring material is oxidized due to oxidizing atmosphere or an interlayer insulating film. Thus, only a temperature of 400° C. or less is applied to prevent such oxidation. A wafer is often subjected to a plasma atmosphere to perform etching at the processing temperature of such about 400° C. and deposit an insulating film while embeddability is being maintained. Also the wafer is subjected to a plasma atmosphere even at sputtering of a metal. In these plasma atmospheres, accelerated ions or electrons collide with the wafer so that electrical charges are injected into the wafer.
There is a low possibility that since a majority of electrical charges injected into the wafer flow into a support substrate if the wafer is of a normal bulk wafer, a device will charge up. Since, however, an SOI (Silicon On Insulator) wafer has a buried oxide film (BOX (Buried Oxide) oxide film) formed between a support substrate and an SOI layer on the surface of the wafer, the charges that have flown from the wafer will produce a concentration of electric field at an insulative weak point of an element or device, thus degrading reliability and breaking down an insulating film.
In the conventional semiconductor process, a gate insulating film has been thinned with miniaturization. A gate electrode per se is isolated from a silicon (Si) substrate with a gate insulating film interposed therebetween. When the charges caused by the plasma atmosphere are stored upon etching, there is a fear that the thin gate insulating film is broken down. Therefore, an apparatus used in gate etching and sidewall (Side Wall) etching is designed to such a mechanism that the charges become hard to flow into the wafer. Since high-temperature heat treatment is enabled if polysilicon is used as a gate material, the deposition of an interlayer insulating film using an LP-CVD (Low Pressure Chemical Vapor Deposition) apparatus (deposition temperature: 700° C. to 800° C.) or the like free of plasma damage and excellent in embeddability is common.
As a method for preventing damage due to charge up caused upon formation of Al wiring, for example, a conventional document has proposed a method for forming a wiring pattern across a grid line after an exposed portion has been provided in a silicon substrate on the grid line, thereby to form a current path that leads to the substrate.
There have also been proposed several methods such as a method for providing a conductive path between an SOI layer and an Si support substrate isolated by a BOX oxide film in the SOI wafer to thereby control a substrate potential. A patent document 2 has proposed a method for forming a substrate contact in a buried oxide film that insulates an SOI layer and an Si support substrate from each other. A method for forming a short-circuit conductor for bringing an Si support substrate and an SOI layer into conduction in the neighborhood of a scribe-intended region has been proposed by a patent document 3. A patent document 4 has proposed a method for cutting a scribe line to thereby bring an Si support substrate and an SOI layer disposed above a buried oxide film.
LP-CVD free of a fear of charging damage is principally used in the deposition of an interlayer insulating film in a transistor forming process. On the other hand, an AP-CVD (Atomospheric Pressure Chemical Vapor Deposition) apparatus capable of performing deposition at a relatively low temperature, begins to be developed in recent years. However, the preset apparatus involves a problem about embeddability. Dry etching is mainstream upon gate etching. An apparatus is used which makes it hard to store electrical charges in a thin gate insulating film.
However, charging damage caused by a process is not so taken into consideration at metal sputtering for a wiring process subsequent to the formation of a transistor and dry etching.
FIG. 6 is a diagram schematically showing, by a sectional partly cut area, the manner in which electrical charges are stored by deposition of a metal layer by sputtering in a wiring process employed in a method for manufacturing a semiconductor device using an SOI wafer 200. In the drawing, the left end corresponds to a wafer edge 222. A semiconductor element is not formed in a wafer edge region 224 corresponding to a peripheral region extending to about 5 mm in the direction (right direction here) of the center of the wafer as viewed from the wafer edge. A region near the wafer center from the wafer edge region 224 corresponds to a device forming region 226, where various devices are formed.
Here, the SOI wafer 200 comprises an Si support substrate 202, a BOX oxide film 204 and an SOI layer 206. The Si support substrate 202 and the SOI layer 206 are insulated from each other by the BOX oxide film 204 used as a buried oxide film. Individual devices formed in the SOI wafer 200 are separated from one another by device-to-device isolation regions 208. A detailed description thereof is omitted in FIG. 6, and a gate insulating film 210 and a gate electrode 212 are shown in FIG. 6. An interlayer insulating film 214 is deposited on the upper side of the SOI wafer 200 formed with the devices. A contact 216 for connecting to an upper wiring is formed over the gate electrode 212.
A conductive layer 218 to be subsequently formed as each wiring by patterning is deposited on the upper surfaces of the interlayer insulating film 214 and the contact 216. At this time, electrical charges (indicated by arrows as the injection 220 of the charges by sputtering in the drawing) on the wafer surface produced during sputtering are in danger of being stored in the corresponding device through the contact 216. These electrical charges will degrade insulative weak points and cause dielectric breakdown. Since the electrical charges stored in the device are isolated by the buried oxide film, there are no places to allow the charges to escape, and there is a possibility that stress greater than an assumed electric field will be applied, thus degrading reliability of each device.
The device formed according to such a process results in an unstable yield due to the occurrence of a leak current by dielectric breakdown and fluctuations in transistor characteristics.
Thus, the present invention aims to reduce storage of electrical charges by metal sputtering or dry etching, which occurs due to an insulating layer being buried in between as in an SOI wafer, thereby to prevent a reduction in device's yield due to charge up.